(1) Field of the Invention
The present invention relates to a semiconductor memory which is mounted on a semiconductor device formed on a semiconductor substrate and stores data obtained by arithmetic processing or the like.
(2) Description of the Related Art
With reference to the drawings, hereinafter, description will be given of a conventional semiconductor memory for storing data obtained by arithmetic processing or the like in a semiconductor device.
FIG. 12 is a block diagram showing a configuration of the semiconductor device on which the conventional semiconductor memory is mounted. As shown in FIG. 12, the semiconductor device 1 includes a functional block 2, the semiconductor memory (hereinafter, simply referred to as “memory”) 3 having a function of storing data, an analog-to-digital (hereinafter, abbreviated as “A/D”) converter 4, a logic circuit 5, and a pad 6.
Specifically, the semiconductor device 1 is configured by the functional block 2 and the memory 3. The functional block 2 is configured by the logic circuit 5 and the A/D converter 4. The logic circuit 5 is electrically connected to the A/D converter 4 and the memory 3. The pad 6 is connected to the A/D converter 4.
With reference to the drawings, next, description will be given of data correction sequences in the semiconductor device 1 configured as described above.
FIG. 13 shows data inversion sequences in the semiconductor device 1. FIG. 14 is a timing chart showing waveforms of signals received by the memory 3.
In a case where the logic circuit 5 recognizes a bit to be corrected in data stored in the memory 3, first, the logic circuit 5 transfers a read command to the memory 3 to acquire read data. Then, the logic circuit 5 prepares corrected appropriate data as write data based on the read data and information about an inverted bit. Next, the logic circuit 5 executes a write command based on the appropriate data to write the data to the memory 3. That is, conventionally, the data inversion sequences in the memory 3 include a read operation, a standby time and a write operation.
In a case where the aforementioned semiconductor device 1 is used for reading data from a storage medium such as an optical disc, and then storing the read data, occasionally, data different from intended data is stored in the memory 3 due to an influence of noise. In order to avoid an erroneous operation due to the aforementioned disadvantage, there is prepared a parity bit for error correction such as an ECC; thus, an inverted bit can be identified.
As described above, in the semiconductor device 1, the memory 3 (e.g., a DRAM) reads erroneous data therefrom in the read operation, and the logic circuit 5 inverts an erroneous bit to prepare appropriate data and writes back the appropriate data to the memory 3 in the write operation. Consequently, it takes much time to perform error correction on data.
Therefore, there arises a problem that data stored in the memory 3 cannot be subjected to error correction at a high speed.